The present invention relates to a memory access control circuit for controlling dynamic RAM access and, more particularly, to a memory access control circuit for efficiently accessing a dynamic RAM having a page or static column mode.
An address is input to a dynamic RAM (to be referred to as a DRAM hereinafter) such that address data is divided into upper and lower address signals nd these signals are time-division multiplexed. The access time in the DRAM data read mode is defined by a period required for identifying data after the upper and lower address signals are input to the DRAM. Since each address data is divided into two address signals and these signals are input to the DRAM, the access time is undesirably prolonged.
A CPU or DMA controller tends to access data having successive or adjacent addresses. In this case, data having the same upper address but different lower addresses is frequently accessed.
By utilizing the feature for updating only the lower address, page mode access or static column access is proposed to shorten the DRAM access time. The operation for reading out three address signals (0100).sub.H to (0102).sub.H (FIG. 1), where H represents the hexadecimal notation according to page mode access, will be described with reference to the timing chart of FIG. 2. Upper address (01).sub.H is input to the DRAM. In response to this address, row address strobe signal RAS goes to level "0". All data corresponding to upper address (01).sub.H is read out from memory cells in the DRAM. Lower address (00).sub.H is then input to the DRAM. In response to this, column address strobe signal CAS goes to level "0". Only data corresponding to address (00).sub.H is read out from the DRAM and output outside the DRAM. As a result, data A stored at address (0100).sub.H is read out as output data.
Subsequently, second lower address (01).sub.H is input to the DRAM. In response to this, signal CAS goes to level "0". Since all the data corresponding to address (01).sub.H in the DRAM has been accessed, only the data corresponding to this lower address is selected from the accessed data and output outside the DRAM. Therefore, data B stored at address (0101).sub.H of the DRAM is read out. Similarly, data is sequentially selected and output in response to the lower address inputs and falling of signal CAS to level "0" in synchronism with each lower address input.
According to page mode access, once the upper address input is supplied to the DRAM, only different lower address inputs are supplied thereto to read out desired data. Therefore, the access time for the second and subsequent read operations can be shortened.
Static column access employs the same addressing as that of page mode access. In addition, as shown in FIG. 2, signal CAS is set to be continuously active (level "0") within the period for inputting a plurality of lower addresses. Since the logical level of signal CAS need not be repeatedly changed, data access can be achieved at a higher speed.
In order to achieve high-speed access, page mode access and static column access are based on the assumption that the upper address is not frequently updated. In other words, if the upper address is frequently updated, high-speed access cannot be performed.
A conventional device (e.g., a CPU or a DMA controller) for accessing a memory does not have a function for discriminating whether or not the upper address is updated. As a result, the conventional CPU or DMA controller cannot employ a page mode access or static column access function assigned to the DRAM.